1. Field of the Invention
The present invention relates to a semiconductor device including a bipolar transistor, and a method of fabricating such a semiconductor device.
2. Description of the Background Art
A conventional method of fabrication corresponding to formation of a vertical NPN bipolar transistor will be described with reference to FIGS. 16-26. Impurities are implanted from the main surface of a silicon substrate 1 to form a P type layer 52. Then, a P type embedded layer 3 is formed. N type impurities are implanted into P type layer 52. By annealing, an N type embedded layer 2 is formed. As a result, N type embedded layer 2 is completely surrounded by the P type region in silicon substrate 1, as shown in FIG. 16.
Referring to FIG. 17, an epitaxial grown layer 4 of a low resistance such as approximately 0.1 xcexa9xc2x7cm is formed having phosphorus doped all over the main surface of silicon substrate 1. N type embedded layer 2 and P type embedded layer 3 are respectively diffused towards epitaxial grown layer 4, as shown in FIG. 17. A graph of the impurity concentration distribution at the cross section traversing N type embedded layer 2, i.e. the cross section taken along XVIIIxe2x80x94XVIII in FIG. 17, is shown in FIG. 18. A region corresponding to epitaxial grown layer 4 and silicon substrate 1 are marked along the vertical axes indicating the depth from the surface. A distribution curve 81 indicates the concentration of phosphorus doped into epitaxial grown layer 4, i.e. the concentration of N type impurities. A distribution curve 82 indicates the concentration of the N type impurities implanted into N type embedded layer 2. Since epitaxial grown layer 4 is initially formed having phosphorus doped, the concentration of the impurity is constant irrespective of the depth, as appreciated from distribution curve 81 of FIG. 18. The reason why distribution curve 81 slightly protrudes into silicon substrate 1 is due to the fact that a portion of the impurities formerly included in epitaxial grown layer 4 diffuses into the under-contacting silicon substrate 1. The N type impurities implanted initially into N type embedded layer 2 diffuse into epitaxial grown layer 4. Thus, distribution curve 82 of FIG. 18 exhibits intrusion towards epitaxial grown layer 4.
A graph of the impurity concentration at a region where there is no impurity layer in FIG. 17, i.e. the cross section along XIXxe2x80x94XIX is shown in FIG. 19. In FIG. 19, only a distribution curve 81 is present since there are only N type impurities, i.e. phosphorous, doped into epitaxial grown layer 4.
Referring to FIG. 20, impurities are implanted to predetermined regions in epitaxial grown layer 4 to form a P type isolation diffusion layer 6 and an N type collector leading layer 7. Then, a field oxide film 5 is formed by LOCOS (local oxidation of silicon). Then, an oxide film 8 is formed at the collector contact region, as shown in FIG. 20.
Referring to FIG. 21, a polysilicon layer is formed all over the surface, followed by ion-implantation of boron of high concentration. Unrequired portions are removed from the polysilicon layer, resulting in an external base 9 by the remaining polysilicon layer. An interlayer oxide film 10 is formed so as to cover the entire surface including external base 9. Etching is effected to form an opening through interlayer oxide film 10 and external base 9 of polysilicon so as to expose epitaxial grown layer 4. This opened portion corresponds to an emitter opening 27. Emitter opening 27 is filled with boron to form an intrinsic base 11, as shown in FIG. 21.
Referring to FIG. 22, an oxide film spacer 12 is formed to electrically insulate and block external base 9. Boron is diffused from external base 9 into epitaxial grown layer 4 by thermal treatment, whereby a P type diffusion layer 13 shown in FIG. 22 is formed.
Referring to FIG. 23, a polysilicon layer is formed so as to cover emitter opening 27. Arsenic is implanted into the polysilicon layer, followed by annealing, whereby arsenic is diffused into intrinsic base 11 to form an N type diffusion layer 14. The unrequired portion of the polysilicon layer is removed. By the remaining portion of the polysilicon layer, an emitter electrode 15 shown in FIG. 23 is formed. Oxide film spacers 16A and 16B are formed so as to cover respective sidewalls of emitter electrode 15 and external base 9, respectively. By forming a CoSi film 17 so as to cover the top surface of external base 9 and N type collector leading layer 7, the parasitic resistance of emitter electrode 15 and external base 9 is reduced.
Referring to FIG. 24, an interlayer insulating film 20 is formed. A contact hole is formed in interlayer insulating film 20. A contact plug 21 is formed by filling the contact hole with a conductor. By connecting the top faces of contact plug 21 with each other through an aluminium line 22, a vertical NPN bipolar transistor of FIG. 24 is provided.
A cross sectional view of a further larger range is shown in FIG. 25. Here, the so-called passive element such as the inductor and capacitor are included here. A polysilicon resistor 18 is included as shown in the cross sectional view of FIG. 25. Polysilicon resistor 18 is adjusted to a desired resistance by controlling the dopant concentration before interlayer insulating film 20 is formed. Polysilicon resistor 18 is also classified as a passive element. An interlayer insulating film 23 is formed above aluminium line 22. In the region where a MIM (Metal Insulator Metal) capacitor 31 is formed, an opening is formed deep into interlayer insulating film 23 so that the top face of aluminium line 22 is exposed. A capacitor dielectric film 24 is formed so as to cover the inner face of that opening and the top plane of interlayer insulating film 23. As shown in FIG. 26, an aluminium line 25 is arranged at the top face of capacitor dielectric film 24 above interlayer insulating film 23. A vertical hole is formed in advance at a predetermined position in interlayer insulating film 23, arriving at aluminium line 22. When aluminium line 25 is formed, these vertical holes are filled with a conductor to establish electrical connection between aluminium line 22 and aluminium line 25. By working on aluminium line 25, the upper electrode of MIM capacitor 31, a spiral inductor 32 and a pad 33 are formed. Then, a nitride film 26 that becomes a protection film is grown thereon. An opening is formed in pad 33. Although not shown, a metal film is formed at the backside of silicon substrate 1.
Although a method of fabricating a vertical NPN bipolar transistor is shown as conventional art, horizontal PNP bipolar transistors and CMOS transistors are often formed on the same chip in addition to the vertical NPN bipolar transistor generally. Furthermore, although only a polysilicon resistor, a MIM capacitor and a spiral inductor are enumerated as passive elements here, other elements such as a MOS capacitor and a Shottky diode are also formed on the same substrate.
Here, a bipolar transistor including only a junction in silicon has been described as a vertical NPN bipolar transistor. Additionally, a hetero junction bipolar transistor employing SiGe for the base (Silicon Germanium-Hetero Bipolar Transistor: SiGe-HBT) shown in FIG. 27 is also known. This type of bipolar transistor has a silicon layer 61, a SiGe layer 62, and a silicon layer 63 layered respectively by epitaxial growth in order on epitaxial grown layer 4. Silicon layer 61 includes phosphorus, and functions as a collector layer. SiGe layer 62 includes boron, and functions as a base layer. Silicon layer 63 includes boron. An external base 64 extends from either side thereof. External base 64 corresponds to the junction between the intrinsic base layer and the base electrode, functioning as a bipolar transistor. External base 64 includes boron in high concentration in order to reduce the resistance. On silicon layer 63 is provided a polysilicon layer 15 including arsenic as the impurity. The diffusion of arsenic from polysilicon layer 15 towards silicon layer 63 causes formation of an N type diffusion layer 14. The combination of N type diffusion layer 14 and polysilicon layer 15 corresponds to an emitter layer. The details are described in xe2x80x9cSiGe HBT Technology: A New Contender for Si-Based RF and Microwave Circuit Applicationsxe2x80x9d by John. D. Cressler in IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, Vol. 46, No. 5, May 1998.
The above conventional application method has problems set forth below. In a device including a vertical bipolar transistor, an epitaxial grown layer of a low resistance such as 0.1-1.0 xcexa9xc2x7cm having N type impurities doped to function as a collector layer is formed all over a silicon substrate to a thickness of approximately 0.6-3.0 xcexcm. Therefore, an epitaxial grown layer of low resistance will also be formed below elements other than the transistor, i.e., under the passive elements.
A structure of the passive element region is shown in the cross sectional view of FIG. 28 in a simplified manner to describe the problem therein. The example of FIG. 28 includes an aluminium line 22, representative of passive elements of various types. An epitaxial grown layer 4 of low resistance is formed on silicon substrate 1. Thereon, a field oxide film 5, and then an interlayer insulating film 20 are formed. Aluminium line 22 is arranged on interlayer insulating film 20. A back electrode 35 is formed at the back side of silicon oxide film 1. A simplified equivalent circuit corresponding to such a structure is shown in FIG. 29. A parasitic capacitance C1 is generated between aluminium line 22 and epitaxial grown layer 4 of low resistance. Such a parasitic capacitance induces a charging and discharging current flow during the operation of the semiconductor device to cause loss therein.
Conventionally, the countermeasure of employing a silicon substrate of high resistance for the semiconductor substrate has been employed to prevent parasitic capacitance between the passive element and the semiconductor substrate. However, the problem of parasitic capacitance between a passive element and an epitaxial grown layer of low resistance could not be solved by just using a silicon substrate of high resistance. To solve this parasitic capacitance, an approach of removing the epitaxial grown layer of low resistance formed under the passive element by etching can be considered. However, this method leaves a distinct step between the region where the epitaxial grown layer is removed and the region where the epitaxial grown layer is not removed. This distinct step causes the problem that the exposure margin is insufficient at the subsequent transfer process. Although this distinct step can be alleviated by providing an oxide film or the like, such an additional process will increase the number of fabrication steps.
In view of the foregoing, an object of the present invention is to provide a semiconductor device obviating the problem of a distinct step in a transfer process, and absent of parasitic capacitance between the passive element and epitaxial grown layer of low resistance, and a fabrication method of such a semiconductor device.
According to an aspect of the present invention, a semiconductor device includes a semiconductor substrate having a main surface with first and second regions defined in plane, a first layer formed on the main surface, and a second layer formed above the first layer, and having a resistance lower than the resistance of the first layer. The semiconductor device includes a bipolar transistor at the first region, and a passive element at the second region. The second layer is arranged so as to cover at least the first region and avoid at least a portion of the second region. By such a structure, the region below the passive element in the second region is absent of the second layer of low resistance. Therefore, the parasitic capacitance at the region where the passive element is arranged can be reduced. Furthermore, by adjusting the ratio of the thickness of the first layer and the second layer, the stepped portion generated by the absence and presence of the second layer can be reduced.
According to another aspect of the present invention, a method of fabricating a semiconductor device includes the steps of forming an impurity-containing portion at a predetermined region at a main surface of a semiconductor substrate, forming a first layer so as to cover the impurity-containing portion from the upper side by epitaxial growth at a high temperature of at least 900xc2x0 C., and forming a second layer having a resistance lower than the resistance of the first layer at an upper side of the first layer by epitaxial growth. By employing such a method, impurity diffusion can be directed from the impurity-containing portion to a predetermined region in the first layer during the epitaxial growth of the first layer.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.